1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, more particularly it relates to a non-volatile semiconductor memory having dual gate electrodes.
2. Description of the Related Art
A non-volatile semiconductor memory device is made to handle the write and read signals by shifting the threshold voltage by the charge existing in a charge storing mechanism formed in the insulating film.
For example, where the electrons are stored in the charge holding mechanism of a non-volatile semiconductor memory device of the N-type Metal-Oxide-Silicon (MOS) type, the threshold voltage is shifted to a positive direction. At the time of a read operation, a voltage is applied to the memory cell in question, but since the threshold voltage is larger than this applied voltage due to the electrons stored in this charge holding mechanism, the current flowing through the bit line is reduced. Conversely, where no electrons are stores in the charge holding mechanism or positive holes are stored, the threshold voltage is shifted to a negative direction, therefore the amount of the current flowing at the time of a read operation becomes large.
In this way, the basic operating principle of the nonvolatile semiconductor memory device lies in the use of the difference occurring in the current flowing through the transistor and making the magnitude of the current flowing at the time of a read operation correspond to the binary information.
Usually, the memory transistors are formed by a bulk process, impurities are introduced into channel parts and other portions, punch through or leakage between elements is prevented from occurring, and, at the same time, the threshold value is controlled.
However, disadvantages are caused due to the formation of the insulating film and the ion "implantation. To fix these, a high temperature heating step is necessary. Therefore, it is difficult to optimize the distribution of the impurities in the elements.
Further, in the sub-0.1 .mu.m generation of gate lengths, the statistical fluctuation in the concentration of the impurities to be introduced becomes relatively large - so much so as to exert an influence upon the actual device. Therefore, the control of the threshold voltage becomes further difficult.
Especially, the statistical fluctuation of the concentration of the impurity of the channel part is directly related to the fluctuation of the threshold voltage of the element, therefore a uniform circuit operation no longer can be carried out. Thus it has been said that the 0.1 .mu.m generation may become the limit of miniaturization of the bulk type of MOS transistors.
In order to avoid this, a MOS transistor having a configuration in which two gates sandwich a channel having a low impurity concentration using a silicon on insulator (SOI) structure (structure in which a silicon monocrystalline layer is isolated via an insulating layer) or the like (a so-called XMOS transistor) has been proposed.
Since the gate electrode used for writing/erasing and the gate electrode accessed at the time of a read operation are the same, the voltage is applied both to the gate electrodes of the transistor accessed at the time of reading data and the non-selected transistors connected to the same word line WI, W2, or the like. For this reason, the non-selected memory cells also enter into a weak writing state whereby the data is destroyed. This disadvantage, called the "reading disturbance", has been difficult to eliminate.
Further, the closer one gets to this generation of miniaturization, the more it is required that the program voltage of the non-volatile semiconductor memory device be reduced as much as possible and the more it is required to reduce the thickness of the insulating layer and the ferroelectric film constituting part of the charge holding mechanism. However, this conversely aggravates the effect of the reading disturbance.
Further, since the memory unit, the peripheral circuits, and the other circuits (logic etc.) have different structures of gate insulating layers, it is necessary to form the gate electrodes divided in two or three steps.
Further, the semiconductor layer is in an electrically floating state since it is completely surrounded by an insulator. For this reason, charges which are not absorbed by the source (for example, positive holes in the case of an NMOS) among the charges generated during the operation of the element, for example, the charges electrolytically dissociated due to collision at the drain end, are stored in the semiconductor layer, which changes the potential.
Such a change of the potential changes the threshold voltage and consequently becomes a cause preventing a uniform circuit operation.